ECE/CS 5740/6740 - CAD of Digital Circuits and Systems

CAD of Digital Circuits - Logic Synthesis and Optimization

Spring 2026

M, W, F, 10:45am - 11:35am, MEB 2325

Instructor, TA and Office Hours

Instructor: Priyank Kalla

Email: kalla@ece.utah.edu

Office: MEB 4112

Office Hours: TBD

TA: TBD

Course Downloadables

Class organization, grading, etc.

Course Syllabus

Course Objective and Description

Canvas access and Class Mailing/discussion List

I have setup Canvas for all the four sections (ECE/CS 5740/6740) of this course. The Canvas page can be accessed: from this URL.

Important: All the course content can be accessed through THIS website. Canvas will be used for discussions on any course-related topic, tool usage, and also for uploading programming assignments. I may upload some lecture videos also on the Canvas page.

Textbook

Title: Logic Synthesis and Verification Algorithms, by Profs. Gary Hachtel and Fabio Somenzi. Publisher: Springer. The bookstore is working on making an electronic copy or a coursepack available for the students.

This is what the book looks like.

Grading Policy

Homeworks and Programming Assignments: 20%

Mid-Term Exam I: 15%

Mid Term Exam II: 15%

Final Exam: 25%

Final Project: 25%

Late HW Policy

There will be around 6 HWs. Each HW will have a due date by which it should be submitted. However, late submissions will be accepted for 3 extra days with a flat 20% penalty. Canvas site will be available to accept the HW for 3 more days. [Of course, exceptions can be made for medical issues, unforseen circuistances...]

Other guidelines

Spring 2026 Price College of Engineering Guidelines: here.

Students are bound by the ECE academic misconduct policy and the University's Student Code. Cheating on homeworks and projects or plagiarizing constitute academic misconduct in this course and will result in academic sanction. These include copying solutions from other students, submitting someone else's code or experiments as yours, copying the work of others without crediting it to them. Learning from each other is encouraged, but in the end you have to solve the problems on your own, and run your own experiments and make your own observations from those experiments. Academic misconduct on any assignment will result in a sanction in this course up to failing the course. The sanctions are the following:

First offense on a homework/laboratory assignment will result in a zero on the assignment.

Second offense will result in failure of the course and an incident report will be submitted to the department and college.

Lecture Notes and Slides

01/05: An Introduction to CAD and Synthesis . A few years ago, I gave a crash course lecture: a basic introduction to the course. It was targeted for those who don't really have a good idea about what Logic Synthesis is about. Uploaded here for your perusal.

At a high-level, we will organize the course according to the following set of topics.

Basic Boolean algebra and operations, and intro to covering problems

01/05 - 01/07: Getting started: Slides on Boolean algebra and Boolean operations slides_bool_alg.pdf

01/07: Boolean algebra, implementation cost of Boolean functions and basic Boolean operations

Shannon's expansion, Boolean difference, Consensus, Smoothing, Unate and Binate functions.

Introduce the idea of Binary Decision Diagrams as a graph-based data-structure for efficient Boolean function representation and manipulation.

Here are some notes on Generalized cofactors, and how they can be used for Boolean function decomposition.
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BDDs and SAT Solvers as core data-structures and synthesis engines
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Two Level Logic and Heuristic Optimization
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Algebraic Kernel-based Multi-level Logic Optimization
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Boolean Decomposition for Multi-level Logic Optimization
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Sequential Logic Optimization
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Technology Mapping
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Logic Synthesis for post-CMOS Technologies
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Course conclusion

Reading Assignments

For the week 01/05-01/09: Chapters 1 and 2 are introductory chapters that give a brief overview of logic synthesis. I suggest the class should read these chapters this week. There is no need to get into the nitty-gritty details, just an overview is what is required.

Homeworks and Programming Assignments

HWs will be assigned after the first week of classes.

Options for Class Projects

Here is a description of class projects that you could pursue. Take a look. I will keep on updating this document as and when I find more time and more information. Class project document latest update: Feb 20, 2019..

Many of these projects can easily turn into MS thesis or projects.

Software, Tools, Benchmarks

Binary Decision Diagrams: The ROBDD Package

To download the Colorado Decision Diagram (CUDD) package

David Kebo had a good website: The CUDD Package, BDD and ADD Tutorials: https://davidkebo.com/cudd
Here is the documentation for the CUDD package: cudd.pdf.
You can also get it from Githib: https://github.com/ivmai/cudd .

Boolean SAT tools

Many SAT tools are available in public domain. For our purposes, Lingeling, PicoSAT and/or zCHAFF will suffice.

Here is the picoSAT website from where you can download and compile the source code. MAC OS users can find one through MacPorts.
Here is the Lingeling website
Here is the zchaff website from where you can download and compile the source code.
Here is a linux binary that I use zchaff on the CADE machines.
Here is a sample CNF file in the DIMACS CNF format that these SAT solvers can take as input.
Here is a blif2cnf perl script. Feel free to use it.

Linear Program

Download LPSolve - an integer-linear program solver (executable compiled on LINUX machines) and some sample .lp files:

exam_table_cover.lp .
Another lp example which is infeasible.

SIS-related materials

Espresso - Two-level logic minimizer

Espresso, compiled for Linux download Espresso

Espresso manual can be downloaded from at this Berkeley website . BEWARE - there is a whole lot of information here, most of which you don't need right now. Just run 'espresso -h' (h = help) and you'll figure out most of the stuff.

Here is the 3-input majority function written in kiss format.

FSM Minimization and State Assignment

State Minimization Download stamina and an example state machine in fsm.kiss file from here .

Two-Level State Encoding Download Nova

Multi-level Logic Optimization System: SIS

SIS compiled for linux: Download SIS executable

SIS Manual/paper: SIS paper .

STD. Cell Library: lib2.genlib , lib2_latch.genlib

Here are some .blif and .pla files: des.blif , alu4.pla and 9sym.pla .

Here is file script.rugged and script.delay .

Utility packages - arrays, lists, symbol tables - for your projects

Packages: tar'ed and gzipped here .

The ABC tool from Alan Mishchencko, UCB

Go to Alan's website for the ABC synthesis tool and get the ABC tool. This is the most advanced logic synthesis tool (techniques) freely available. Link to Alan's Website is here.

This is an older version of my own personal copy of compiled linux binary of ABC.

Some benchmarks for experimenting with projects

Here is a gzipped tarball of a few benchmark designs that you can use for synthesis experiments and for your class projects.