Books and Book Chapters
Rectification of Arithmetic Circuits with Craig Interpolation
in Finite Fields. Utkarsh Gupta, Irina Ilioaea, Vikas Rao,
Arpitha Srinath, and Priyank Kalla, and Florian Enescu. Invited
chapter in
book
VLSI-SoC: Design and Engineering of Electronics Systems Based on
New Computing Paradigms, Eds. N. Bombieri et al., Springer,
pp. 79-106, 2019.
Emerging Circuit Technologies: An Overview of the Next
Generation of Circuits. R. Wille, K. Chakrabarty,
R. Drechsler, P. Kalla. Invited chapter in book Advanced Logic
Synthesis, Eds. Andre' Reis and R. Drechsler. Springer
Intl. Publishing, pp. 43-68, 2018, ISBN 978-3-319-67295-3.
Design Automation for On-Chip Nanophotonic
Integration. Chris Condrat, Priyank Kalla, and Steve
Blair. Chapter 8 in More than Moore Technologies for Next
Generation Computer Design, Editor: Rasit Topaloglu, Springer,
2015, pp. 187-218.
- The book and the article can be
accessed at Springer's
website
here.
Algebraic Techniques to Enhance Common Sub-Expression Extraction
for Polynomial System Synthesis. S. Gopalakrishnan and P. Kalla. Book
chapter, Chapter 14, pp. 251-265. Book title: Advances in Logic
Synthesis, Optimizations and Applications. Springer, 2011. Editors:
S. Khatri and K. Gulati.
Logic Testing. Invited Article, Wiley Encyclopedia of Electrical
and Electronics Engineering, John Wiley and Sons, Inc., Ed. John
G. Webster, vol. 11, pp. 591-597, 1999.
Journal Publications
Boolean Groebner Basis Reductions on Finite Field Datapath
Circuits using the Unate Cube Set Algebra. Utkarsh Gupta,
Priyank Kalla and Vikas Rao. IEEE Trans. on CAD, vol. 38, issue 3,
pp. 576-588, March 2019.
Efficient Symbolic Computation for Word-Level Abstraction from
Combinational Circuits for Verification over Finite
Fields. Tim Pruss, Priyank Kalla and Florian Enescu. IEEE
Trans. on CAD, vol. 35, No. 7, pp. 1206-1218, July 2016.
Crossing-aware Channel Routing for Integrated Optics. C. Condrat,
P. Kalla, and S. Blair. IEEE Trans. on CAD, vol 33, no 5, pp. 814 - 825,
special section on Optical Interconnects, June 2014.
Efficient Groebner Basis Reductions for Formal Verification of
Galois Field Arithmetic Circuits. J. Lv, P. Kalla and
F. Enescu. IEEE Transactions on CAD, vol 32, issue 9, pp. 1409 -
1420, Sept. 2013.
Simulation Bounds for
Equivalence Verification of Polynomial Datapaths using Finite Ring
Algebra . Namrata Shekhar, Priyank Kalla,
M. Brandon Meredith and Florian Enescu. IEEE Trans. on VLSI, special
section on Design Validation
and Verification, pp. 376-387, vol. 16, issue 4, April 2008.
Optimization of
Polynomial Datapaths using Finite Ring Algebra. Sivaram
Gopalakrishnan and Priyank Kalla. ACM Trans. on Design Automation of
Electronic Systems (ACM-TODAES), vol 12, issue 4, article 49,
September 2007.
- This paper is a receipient of the 2009 ACM TODAES
best paper award.
Equivalence Verification of
Polynomial Datapaths using Ideal Membership Testing. Namrata
Shekhar, Priyank Kalla and Florian Enescu. IEEE Trans. on CAD,
pp. 1320-1330, vol. 26, number 7, July 2007.
Taylor Expansion Diagrams: A
Canonical Representation for Verification of Dataflow Designs
. Maciej Ciesielski, Priyank Kalla and Serkan Askar. IEEE
Transaction on Computers, Vol. 55, Issue 9, pp. 1188-1201,
Sept. 2006.
BDD-Based Logic Synthesis for LUT-Based
FPGAs. Navin Vemuri, Priyank Kalla, Russell Tessier. ACM Transaction
on Design Automation of Electronic Systems, Special Issue on
Reconfigurable Systems. Oct 2002.
A Comprehensive Approach to the
Partial Scan Problem using Implicit State Enumeration. Priyank
Kalla and Maciej Ciesielski. IEEE Transaction on CAD, July 2002.
Strategies for Solving the Boolean Satisfiability Problem using
Binary Decision Diagrams. Journal of Systems Architecture, Euromicro
Journal, vol. 47/6, pp. 491-503, September 2001.
Conference Publications
An Algebraic Approach to Partial Synthesis of Arithmetic
Circuits, B. Sampathkumar, R. Das, B. Martin, F. Enescu, and
P. Kalla. Accepted, to appear in the 30^{th} Asia/South
Pacific Design Automation Conference (ASPDAC), Tokyo, Japan 2025.
Design-for-Test for
Silicon Photonic Circuits, P. Agnihotri, P. Kalla and
S. Blair. Accepted, to appear in Proc. IEEE Intl. Test
Conference, Nov. 2024.
Selecting Rectification
Targets for Patching Buggy Circuits, R. Das and
P. Kalla. IEEE Intl. Symposium on VLSI Design and Test (VDAT)
September 2024.
Logic Synthesis from
Polynomials with Coefficients in the Field of Rationals,
B. Sampathkumar, B. Martin, R. Das, P. Kalla and F. Enescu. IEEE
Intl. Symp. on Multivalued Logic, ISMVL 2023.
Abstractions for Modeling the Effects of Wall Surface
Roughness in Silicon Photonic Microring Resonators, Pratishtha
Agnihotri, Lawrence Schlitt, Priyank Kalla and Steve Blair, IEEE
Latin American Test Symposium, LATS 2023.
Transfer-Matrix
Abstractions to Analyze the Effect of Manufacturing Variations in
Silicon Photonic Circuits, Pratishtha Agnihotri, Priyank
Kalla and Steve Blair, IEEE Intl. Test Conf. India (ITC India),
pp. 1-8, 2022.
Rectification of Integer
Arithmetic Circuits using Computer Algebra Techniques, V. K. Rao,
H. Ondricek, P. Kalla, F. Enescu, IEEE Intl. Conf. on Computer
Design (ICCD) 2021.
Algebraic Techniques for
Rectification of Finite Field Circuits, V. K. Rao,
H. Ondricek, P. Kalla, F. Enescu, IEEE/IFIP Intl. Conf. on VLSI
(VLSI-SoC) 2021.
On the Rectification of Finite Field Arithmetic Circuits
using Computer Algebra Techniques, V. K. Rao, H. Ondricek,
P. Kalla and F. Enescu. Intl. Workshop on Logic and Synthesis,
2021.
Word-Level Multi-Fix
Rectifiability of Finite Field Arithmetic Circuits,
V. K. Rao. I. Ilioaea, H. Ondricek, P. Kalla, F. Enescu. IEEE/ACM
Intl. Symp. Quality Electronic Design, April 2021.
Exploring Algebraic Interpolants
for Rectification of Finite Field Arithmetic Circuits using
Groebner Bases , U. Gupta, P. Kalla, I. Ilioaea,
F. Enescu. In Proc. IEEE European Test Symposium, May 2019.
Post-Verification Debugging and
Rectification of Finite Field Arithmetic Circuits using Computer
Algebra Techniques. V. K. Rao, U. Gupta, I. Ilioaea,
A. Srinath, P. Kalla and F. Enescu. In
Proc. Formal Methods in Computer-Aided Design (FMCAD), November
2018.
On the Rectifiability of
Arithmetic Circuits using Craig Interpolants in Finite
Fields. U. Gupta, I. Ilioaea, V. Rao, A. Srinath, P. Kalla,
and F. Enescu. In Proc. IFIP/IEEE/AICA
Intl. Conf. on VLSI (VLSI-SOC), October 2018.
- Best Paper Award Candidate
Craig Interpolants in
Finite Fields using Algebraic Geometry: Theory and
Application. U. Gupta, I. Ilioaea, P. Kalla, F. Enescu,
V. Rao, A. Srinath. In proc. Intl. Workshop on Logic and Synthesis
(IWLS), 2018.
Boolean Gröbner Basis
Reductions on Datapath Circuits using the Unate Cube Set
Algebra. Utkarsh Gupta, Priyank Kalla and Vikas
Rao. Intl. Workshop on Logic and Synthesis, IWLS 2017.
- Best Paper with Student as First Author Award
Word-Level Traversal of Finite State
Machines using Algebraic Geometry. Xiaojun Sun, Priyank Kalla
and Florian Enescu. IEEE Intl. Workshop on High-Level
Design Validation and Test, 2016, pp. 142-149.
Finding Unsatisfiable Cores
of a Set of Polynomials using the Gröbner Basis
Algorithm. Xiaojun Sun, Irina Ilioaea, Priyank Kalla and
Florian Enescu. Intl. Conf. Principles and
Practise of Constraint Programming, CP 2016.
A
Methodology for Thermal Characterization Abstraction of Integrated
Opto-Electric Layouts. Lawrence Schlitt, Priyank
Kalla and Steve Blair. In Proc. Intl. Conf. on
VLSI Design, India, pp. 270-275, Jan 2016.
DA Vision 2015: From Here to Eternity. M. Potkonjak,
D. Chen, P. Kalla and S Levitan. Invited paper in special
session, in IEEE/ACM Intl. Conf. on CAD (ICCAD) 2015.
Formal Verification of Arithmetic Datapaths using Algebraic
Geometry and Symbolic Computation. Invited tutorial
presented at the joint session of SAT, DIFTS and FMCAD 2015
conferences.
Formal Verification of Sequential Galois Field Arithmetic
Circuits using Algebraic Geometry. Xiaojun Sun, Priyank Kalla, Tim
Pruss, Florian Enescu. In IEEE/ACM Design Automation and Test in
Europe Conference (DATE), pp. 1623 - 1628, March 2015.
Thermal-Aware Synthesis of Integrated Photonic Ring
Resonators. Chris Condrat, Priyank Kalla and Steve Blair. In
proceedings of the Intl. Conf. on CAD (ICCAD), pp. 557 - 564, Nov. 2014.
Equivalence Verification of Large Galois Field Arithmetic
Circuits using Word-Level Abstraction via Groebner Bases. Tim Pruss,
Priyank Kalla and Florian Enescu. In the 51st
Design Automation Conference (DAC), pages 1-6, June 2014. The paper
can be obtained from
the ACM Digital
Library database.
Crossing-Aware Channel Routing for Photonic Waveguides.
C. Condrat, P. Kalla and S. Blair. In Proc. IEEE
Intl. Mid-West Symposium on Circuits and systems (MWSCAS)
2013.
- Recepient, best paper award, with a student as first author.
Channel Routing for Integrated Optics.
C. Condrat, P. Kalla and S. Blair. In Proc. ACM/IEEE
System-Level Interconnect Prediction Workshop 2013.
A Methodology for Physical Design Automation for Integrated
Optics. C. Condrat, P. Kalla and S. Blair. In Proc. 55th IEEE
Intl. Midwest Symposium on Circuits and Systems (MWSCAS), 2012,
pp. 598-601.
Efficient Groebner Basis Reductions for Formal Verification of
Galois Field Multipliers. J. Lv, P. Kalla, and F. Enescu. In
Proceedings Design, Automation and Test in Europe Conf. (DATE) 2012,
Dresden, Germany, pp. 899-904.
Formal Verification of Galois Field Multipliers using Computer
Algebra Techniques. J. Lv and P. Kalla. In Proc. Intl. Conf. on VLSI
Design, Jan. 2012, Hyderabad, India, pp. 388-393.
Verification of Composite Galois Field Multipliers over GF(
(2^m)^n ) using Computer Algebra Techniques. J. Lv, P. Kalla and
F. Enescu. In Proc. Intl. High-Level Design Validation and Test
Workshop (HLDVT) 2011.
Logic
Synthesis for Integrated Optics. C. Condrat, P. Kalla, S. Blair. In
Proc. ACM Great Lakes Symposium on VLSI (GLS-VLSI) 2011, pp. 13 - 18.
Exploring Design and Synthesis in Optical Digital
Logic. C. Condrat, P. Kalla and Steven Blair. In Proc. Intl. Workshop
on Logic and Synthesis (IWLS) 2010.
Algebraic Techniques to Enhance Common Sub-Expression Extraction
for Polynomial System Synthesis. Sivaram Gopalakrishnan and Priyank
Kalla. In Proceedings of the Design Automation and Test in Europe (DATE)
Conf. April 2009. Preliminary slides: PPT file
or the PPTx file .
Verification of Arithmetic
Datapaths using Polynomial Function Models and Congruence
Solving. Neal Tew, Priyank Kalla, Namrata Shekhar and Sivaram
Gopalakrishnan. In Proc. Intl. Conf. on
Computer-Aided Design (ICCAD) 2008, pp. 122-128.
Integrating Common Sub-expression Elimination with Algebraic
Methods for Polynomial System Synthesis. Sivaram Gopalakrishnan and
Priyank Kalla. Intl. Workshop on Logic and Synthesis (IWLS),
pp. 31-37, 2008.
Finding Linear
Building-Blocks for RTL Synthesis of Polynomial Datapaths with
Fixed-Size Bit-Vectors. Sivaram Gopalakrishnan,
Priyank Kalla, M. Brandon Meredith and Florian Enescu. In Proc.
IEEE/ACM Intl. Conf. on Computer-Aided Design (ICCAD), pp. 413-418,
2007.
A Groebner Basis Approach
to CNF formulae Preprocessing. Chris Condrat and Priyank Kalla.
Intl. Conference on Tools and Algorithms for
the Construction and Analysis of Systems (TACAS), O. Grumberg and
M. Huth (Eds.) Lecture Notes in Computer Science (LNCS) vol. 4424,
pp. 618-631, March 2007. [© Springer-Verlag].
Optimization of Arithmetic
Datapaths with Finite Word-Length Operands. Sivaram
Gopalakrishnan, Priyank Kalla and Florian Enescu. In
Proc. Asia/South-Pacific Design Automation Conference (ASP-DAC)
pp. 511-516, 2007.
Guiding CNF-SAT Search by
Analyzing Constraint-Variable Dependencies and Clause Lengths.
Vijay Durairaj and Priyank Kalla. In Proc. High-Level Design
Validation and Test Workshop, HLDVT, pp. 155-161, 2006.
Simulation Bounds for
Equivalence Verification of Arithmetic Datapaths with Finite
Word-Length Operands. Namrata Shekhar, Priyank Kalla, Brandon
Meredith and Florian Enescu. In Proc. Formal Methods in
Computer-Aided Design, FMCAD, pp. 179-186, 2006.
Optimizing Fixed-Size Bit-Vector Arithmetic using Finite Ring
Algebra. Sivaram Gopalakrishnan, Priyank Kalla and Florian Enescu.
In Proc. Intl. Workshop on Logic and Synthesis, IWLS, pp. 110-117,
2006.
Equivalence Verification of
Arithmetic Datapaths with Multiple Word-Length Operands. Namrata
Shekhar, Priyank Kalla and Florian Enescu.
Proceedings of the Design Automation and Test in Europe (DATE) Conf.,
March 2006.
Equivalence Verification of
Polynomial Datapaths with Fixed-Size Bit-Vectors using Finite Ring
Algebra. Namrata Shekhar, Priyank Kalla, Florian Enescu and
Sivaram Gopalakrishnan. In Proceedings of the
Intl. Conf. on Computer-Aided Design ICCAD, Nov. 2005. The powerpoint presentation delivered at
ICCAD .
Exploiting Vanishing Polynomials for
Equivalence Verification of Fixed-Size Arithmetic Datapaths.
Namrata Shekhar, Priyank Kalla, Florian Enescu and Sivaram
Gopalakrishnan. In Proceeding of the
Intl. Conf. on Computer Design ICCD, Oct. 2005. The powerpoint presentation delivered at
ICCD .
Variable
Ordering for Efficient SAT Search by Analyzing Constraint-Variable
Dependencies. Vijay Durairaj and Priyank Kalla. Int'l. Conf. on
Theory and Applications of Satisfiability Testing, F. Bacchus and
T. Walsh (Eds); LNCS 3569, pp. 415-422, SAT 2005. Submitted version
[©
Springer-Verlag].
Dynamic Analysis of
Constraint-Variable Dependencies to Guide SAT Diagnosis . Vijay
Durairaj and Priyank Kalla. International Workshop on High-Level
Design Validation and Test, HLDVT, Nov. 2004.
Exploiting Hypergraph
Partitioning for Efficient Boolean Satisfiability . Vijay Durairaj
and Priyank Kalla. International Workshop on High-Level Design
Validation and Test, HLDVT, Nov. 2004.
Guiding CNF-SAT search via
Efficient Constraint Partitioning . Vijay Durairaj and Priyank
Kalla. International Conference on Computer-Aided Design, ICCAD,
Nov. 2004.
Integrating CNF and BDD Based SAT
Solvers . Sivaram Gopalakrishnan, Vijay Durairaj and Priyank
Kalla. In High-Level Design Validation and Test Workshop, HLDVT 2003.
High-Level Design Verification
using Taylor Expansion Diagrams: First Results. Priyank Kalla,
Maciej Ciesielski, Emmanuel Boutillon, Eric Martin. High-Level Design
Validation and Test Workshop, 2002.
Taylor Expansion Diagrams: A
Compact Canonical Representation with Applications to Symbolic
Verification. Maciej Ciesielski, Priyank Kalla, Zhihong Zeng and
Bruno Rouzyere. Design Automation and Test in Europe, 2002.
Taylor Expansion Diagrams: A
Compact Canonical Representation for RTL Verification. Maciej
Ciesielski, Priyank Kalla, Zhihong Zeng and Bruno Rouzyere. High-level
Design Validation and Test Workshop, 2001.
LPSAT: A Unified Approach to RTL
Satisfiability. Zhihong Zeng, Priyank Kalla, and Maciej Ciesielski.
Design Automation and Test in Europe, 2001.
A BDD-Based Satisfiability
Infrastructure using the Unate Recursive Paradigm Priyank Kalla,
Zhihong Zeng, Maciej Ciesielski and Chilai Huang. Design Automation and
Test in Europe, 2000.
Performance Driven Resynthesis by
Exploiting Retiming-Induced State Register Equivalence Priyank Kalla,
and Maciej Ciesielski. Design Automation and Test in Europe, 1999.
A Comprehensive Approach to the
Partial Scan Problem using Implicit State Enumeration. Priyank Kalla,
and Maciej Ciesielski. International Test Conference, 1998.
Testability of Sequential Circuits
with Multi-cycle False Paths. Priyank Kalla,
and Maciej Ciesielski. VLSI Test Symposium, 1997.