UNIVERSITY OF UTAH
ELECTRICAL AND COMPUTER ENGINEERING DEPT.
50 S CENTRAL CAMPUS DR RM 3280
SALT LAKE CITY, UTAH 84112-9206
Office: Merrill Engineering Building, Rm 2254
Tel.: +801-585-9176 Fax: +801-581-5281
VLSI, asynchronous circuit design and architecture, timing analysis, and formal verification.
|Digital CMOS VLSI provides a fantastic template for creating and engineering communication and control circuitry. Research focuses on architecture, circuit styles, and CAD. The Pentium front end is an example.
|Many second order effects are becoming significant in multi-GHz circuits. A primary DSM effect studied is the variation created through multiple input switching (MIS), and how to generate and prune the worst case vectors. Research is also focused on evaluating and mitigating the effects of process variation.
|Function and timing in circuits are highly interrelated. Verifying the timed behavior using timing variables has been relatively unsuccessful due to computational complexity. The novel Relative Timing research moves timing into the logic domain through relative logic relationships on the ordering of signal transitions. These techniques show order-of-magnitude improvement using SAT methods over the previous best approaches.
|Unclocked circuits have been designed to give significant improvement in performance, latency, and energy over designs with clocks, such as the Pentium front end and the post office chip. Research into correct application of this technology into system VLSI design and SOC integration shows further benefit.
|Current design technology favors design re-use. Integrating modules that run at various frequency and bandwidth requirements require flexible, high throughput, low latency communication networks that can synchronize different frequencies.
Copyright © 2005 - All rights reserved