Patent List for Ken Stevens

Ken Stevens

Associate Professor
University of Utah
Electrical and Computer Engineering
Salt Lake City, UT

e-mail: kstevens@ece.utah.edu


o Kenneth S. Stevens and Dipanjan Bhadra.
Asynchronous Finite State Machines
June 04, 2019. U.S. Patent No. 10,310,994.

o Kenneth S. Stevens and William Lee.
Relative Timed Clock Gating Cell.
Sept. 25, 2018. U.S. Patent No. 10,084,434.

o Kenneth S. Stevens.
Relative Timing Characterization.
April 24, 2018. U.S. Patent No. 9,953,120.

o Kenneth S. Stevens and Dipanjan Bhadra.
Clock Gating with an Asynchronous Wrapper Cell
September 05, 2017. U.S. Patent No. 9,573,486.

o Kenneth S. Stevens and William Lee.
Relative Timed Clock Gating Cell
January 17, 2017. U.S. Patent No. 9,548,736.

o Kenneth S. Stevens and Shomit Das.
Source Asynchronous Signaling
August 04, 2015. U.S. Patent No. 9,100,315.

o Kenneth S. Stevens and Vikas Vij.
Cycle Cutting with Timing Path Analysis
January 29, 2013. U.S. Patent No. 8,365,116.

o Kenneth S. Stevens and Yang Xu.
Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification
November 27, 2012. U.S. Patent No. 8,321,825.

o Kenneth S. Stevens and Yang Xu.
Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification
August 7, 2012. U.S. Patent No. 8,239,796.

o Kenneth S. Stevens.
Method and system for asynchronous chip design
November 22, 2011. U.S. Patent No. 8,065,647.

o Matthew C. Morrise and Kenneth S. Stevens.
Algorithm for finding vectors to stimulate all paths and arcs through an LVS gate
April 29, 2003. U.S. Patent No. 6,557,149

o Kenneth S. Stevens, Shai Rotem, and Ran Ginosar.
``Circuit Synthesis and Verification using Relative Timing''.
November 6, 2001. U.S. Patent No. 6,314,553

o Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Y. Yun, Christopher J. Myers, and Shai Rotem.
``Apparatus and Method for Parallel Processing and Self-Timed Serial Marking of Variable Length Instructions''.
November 2, 1999. U.S. Patent No. 5,978,899

o Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Y. Yun, Christopher J. Myers, and Shai Rotem.
``Apparatus and Method for Self-Timed Marking of Variable Length Instructions Having Length-Affecting Prefix Bytes''.
September 7, 1999. U.S. Patent No. 5,948,096.

o Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Y. Yun, Christopher J. Myers, and Shai Rotem.
``Efficient Self-Timed Marking of Lengthy Variable Length Instructions''.
August 24, 1999 U.S. Patent No. 5,941,982.

o Ran Ginosar, Rakefet Kol, Kenneth S. Stevens, Peter A. Beerel, Kenneth Y. Yun, Christopher J. Myers, and Shai Rotem.
``Branch Instruction Handling in a Self-Timed Marking System''.
August 3, 1999. U.S. Patent No. 5,931,944.

o Bruce W. Suter and Kenneth S. Stevens
``Low Energy Consumption, High Performance Fast Fourier Transform''.
November 3, 1998. U.S. Patent No. 5,831,883

o Alan L. Davis, Shane V Robison, and Kenneth S. Stevens.
``Communication Network For Multiprocessor Packet Communication''.
May 1, 1990. U.S. Patent No. 4,922,408


Comments are welcome. Please send e-mail to kstevens@ece.utah.edu
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