IEEE/ACM Workshop on CAD for
Multi-Synchronous and Asynchronous
Circuits and Systems
(MSCAS) 2012

November 8th, 2012
Hilton San Jose, CA, USA
Registration through ICCAD

Call for Abstracts: Submission deadline Sept 24, 2012; accepted abstracts 20 minute presentation plus poster.
E-mail abstracts to co-chairs listed below.


Many current integrated circuit designs are partitioned into multiple timing domains, allowing each domain to be independently optimized for power and performance. This simplifies timing closure and enables the integration of IP blocks with different timing requirements. One system approach is to use traditional handshaking circuits naturally employ locally generated timing signals that can yield high performance or provide fine-grained activity gating for low power. GALS methods where the asynchrony appears at the level of system integration are another approach.

Multi-synchronous and asynchronous architectures present design challenges and require supportive CAD that arise when departing from the timing methodology and determinism of single frequency synchronous designs. While the departure is already well underway, more systematic CAD support for these designs promises lower power, higher robustness, and better performance. Such a new generation of CAD also enables a much wider base of designers to exploit these advantages.

This workshop provides a forum to discuss current challenges of asynchronous design, how to address the CAD problem, and how to gain penetration of this disruptive technology in industry. This is intended for both technical and industry experts in the asynchronous, GALS, elastic-pipelining, and latency insensitive design communities.

Key Topics


8:15 - 8:30am Welcome and Opening Remarks

Session 1: Timing for multi-synchronous Design
8:30 - 8:55am Ken Stevens (U Utah and GMT)
Multi-Synchronous Relative Timing Providing Order-of-Magnitude Energy Reduction
8:55 - 9:15am Masashi Imai, T. Yoneda (Hirosaki Univ and National Institute of Informatics)
A Floorplan Method for SDI-model-based Asynchronous Circuits to Achieve High Robustness against Delay Variations
9:15 - 9:35am George Engel, J. Ziebold, J. Cox, T. Chaney, and M. Burke (Blendics and SIUE)
Multicycle-Path Challenges in Multi-Synchronous Systems

9:35 - 10:00am

Round Table Discussion

10:00 - 10:30am

Poster Discussions / Morning Break

Session 2: Metastability and Synchronization
10:30 - 10:50am     D. Zar, T. Chaney, Jerry Cox, S. Beer, and R. Ginosar (Blendics and Technion)
Estimating MBTF of Multistage Synchronizers
10:50 - 11:15am Mark Greenstreet (University of British Columbia)
11:15 - 11:35am Ian W. Jones, S. Yang, M. Greenstreet (Oracle and UBC)
SIMMAT: A Metastability Analysis Tool

11:35 - 12:00pm

Round Table Discussion

12:00 - 1:00pm


Session 3: Commercial Silicon and Flow
1:00 - 1:25pm Peter Beerel, invited speaker, (Intel and USC)
Proteus-A: An Asynchronous ASIC Design Flow
1:25 - 1:45pm Arash Saifhashemi, M. Najibi, Y. Cao, C. Qian, G. Wu, A. Mehra, R. Vera, B. Huan, P. Beerel (USC)
A SystemVerilogCSP Front-End to an Asynchronous ASIC Flow
1:45 - 2:10pm Andrew Lines, invited speaker (Intel)
Alta: a guided tour of the most complex asynchronous chip ever

2:10 - 2:30pm

Round Table Discussion

2:30 - 3:00pm

Poster Discussions / Afternoon Break

Session 4: Synchronization and Automation
3:00 - 3:25pm Pranav Ashar, invited speaker (Real Intent)
3:25 - 3:50pm Ran Ginosar, Reuven Dobkin, invited speakers (vSync and Technion)
Multiple-Clock Domain ASIC/FPGA SoCs: Challenges and Solutions
3:50 - 4:15pm Marc Renaudin, Steve Svoboda invited speakers (Tiempo-IC)
Tiempo: A commercial, standards-based flow for designing QDI asynchronous circuits

4:15 - 4:30pm

Session Round Table Discussion

4:30 - 5:00pm

General Multi-Synchronous Round Table Discussion and Posters



Technical Program Committee

Co-chairs:    Ken Stevens, University of Utah
Mark Greenstreet, University of British Columbia

John Bainbridge, Sonics
Gary Delp, Mayo Clinic
Jo Ebergen, Oracle
Steve Furber, University of Manchester
Mike Kishinevsky, Intel
Rajit Manohar, Cornell & Achronix
Doug Morrissey, Octasic
Marc Renaudin, Tiempo IC