ECE/CS 6770
Advanced Digital VLSI Design
Spring 2021


General Information:

Title: ECE/CS 6770 - Advanced Digital VLSI, Spring 2021
Instructor: Ken Stevens, kstevens@ece.utah.edu, MEB 2254, 801-585-9176
Classes: Tu/Th 2:00 - 3:20, online classes and online/CADE lab time
Office Hours: by appointment, contact via email
Web Page: www.eng.utah.edu/~kstevens/6770/
Teaching Asst: None, however my grad students will help
Text Book: Design of High-Performance Microprocessor Circuits by Bowhill & Fox
Prerequisites:    ECE/CS 5710/6710


Course Description:


This course addresses advanced issues in VLSI design, covering the following topics: design methodologies and IP design, CMOS circuit scaling, advanced logic circuit styles, noise sources and signal integrity in digital design, design techniques for dynamic and static power reduction, power supply issues, interconnect analysis, clocking and synchronization, process variation, and performance verification, and timing methodologies. There is a large labs aspect that will give students practical experiment in commercial design flows, design optimization, asynchronous design, and insight into advanced process technologies.

Students are required to have taken ECE/CS 5710/6710 (VLSI Design) or equivalent. The students must be familiar with elementary circuits, basic device physics and logic design, and should have experience with completing a medium scale CMOS design project, including timing, simulation, physical design and layout. Basic familiarity with Verilog, Synopsys, and Cadence design automation tools is assumed. Background in computer design and integrated circuits is very helpful.

Required Textbook:
A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001

Additional Recommended Textbooks:

I. Sutherland, B. Sproull, D. Harris, Logic Effort - designing fast CMOS Circuits, Academic Press, 1999

M. Elrabaa, I. Abu-Khater, Advanced Low-Power Digital Circuit Techniques, Kluwer Academic Publishers, 1997

K. Bernstein, K. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak, N. Rohrer, High Speed CMOS Design Styles, Kluwer Academic Publishers, 1998 T. L Pillage, R. A. Rohrer, C. Visweswariah, Electronic Circuit and System Simulation, McGraw-Hill, 1994

D. Harris, Skew Tolerant Circuit Design, Morgan Kaufmann Publications, 2000

Lab assignments:

Much of the learning in this class will come from lab assignments that will be performed throughout the semester. The goal of the lab assignments is to improve design skills of the students and provide hands-on experience with the advanced topics that we are discussing in class. We will also introduce commercial design flows that include best of breed CAD tools, scripting, and methods to efficiently enable design iteration. The labs will correspond to sections in the lectures and cover many of the issues such as signal integrity, advanced circuit design, performance validation, etc. Each Lab is due after one to two weeks and students are expected to work 9 hours per week out of class.

Homework, Exams:

Homework and exams cover the topics discussed in the lectures. They are not cumulative, and exclusively cover independent sections of the course.

There are various formats the exams can take, from two to four exams per semester. This will be left to the discretion of the class this year.


Grading Policy:


This course provides access to advanced technology information. Some of this information will be accessible only through non-disclosure agreements. If you decide to be granted access to this information and sign the non-disclosure, and then violate the agreement, you will automatically fail this course. This is to protect you, the University, and the companies whom generously have agreed to make this technology available to us.

Exams and homework     50%
Labs and project 50%


Extra Credit Policy: This class uses a Best of Breed philosophy in regard to the CAD tools, process technologies, and libraries that we teach in class. However, due to licensing restrictions, funding, training and maintenance time we have not yet been able to give full access to the best technologies in this course. We do hope to break new ground with some CAD tools and process technologies this year and continue to improve our access to deep submicron technologies and CAD. Extra credit will be given to those who help with the process of improving knowledge and access to advanced technologies. One extra percentage grade point will be awarded for every 1-2 documented hours spent improving our tool setup, up to 5% extra grade points. Qualifying time includes helping with technology and tutorial setup and improvement, basic script creation for new tools, tool debugging, and helping other classmates with tool problems (outside standard usage issues). Documentation time is exempt, but required for the credit. For example, you could help figure out different options for running and analyzing SPICE results, providing scripts and cheatsheets for running FASTSCAN, setting up tools to work on other process technologies, etc. You will need to receive approval from the instructor for this extra credit, and the results must be disseminated to the entire class.


Refer to the College of Engineering Guidelines for more detail on appeals, disabilities, adding, and withdrawing from courses.

Disability: If you have a condition that merits consideration, you must contact the instructor at the beginning of the course.
Add/Drop Policy:   The standard University Policy is applied.
Incomplete Policy:  You cannot get an incomplete unless you have a documented medical or legal emergency or military call.

The College of Engineering also provides counseling services that includes virtual drop-in and individual appointments as well as after hours crisis support.


Detailed Course Information:




Additional Resources:


The CAD tools that we currently have installed and documented are listed on our web page at http://www.eng.utah.edu/cad/.



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