| Online Required Textbook: |
by Erik Brunvand
This is the "lab book" for the class.
This is an online version of an pre-publication draft of the book that has been made available on-line from Dr. Brunvand.
Please respect the copyright and only use this book for the course. Do not distribute any section of this book or make it available on the web!
You will only be able to access this book from the University of Utah web site. If you are off-site you will need to log on using the Utah VPN Client on the web.
Note: The there is an update for the book to map from the version 5 to version 6 of the Cadence desing tool interfaces. You will need to use this in conjunction with the book to efficiently use the tools.
CONTENTS:
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Title page and table of contents |
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Chapter 1: Getting Started |
| Chapter 2: Cadence Design Framework |
| Chapter 3: Composer Schematic Capture |
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Chapter 4: Verilog Simulation |
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Chapter 5: Virtuoso Layout Editor |
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Chapter 6: Spectre Analog Simulation |
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Chapter 7: Cell Characterization |
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Chapter 8: Verilog Synthesis |
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Chapter 9: Abstract Generation |
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Chapter 10: SOC Encounter Place and Route |
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Chapter 11: Chip Assembly |
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Chapter 12: Design Example: TinyMIPS |
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Appendix A: Tool Administration |
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Appendix B: Highlights of the Tools |
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Appendix C: Tool and Startup Scripts |
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Appendix D: MOSIS SCMOS Rev8 Design Rules |
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Appendix E: Technology and Cell Libraries |
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Bibliography and Index |