Ken Stevens Professor UNIVERSITY OF UTAH ELECTRICAL AND COMPUTER ENGINEERING DEPT. 50 S CENTRAL CAMPUS DR RM 3280 SALT LAKE CITY, UTAH   84112-9206 Office: Merrill Engineering Building, Rm 2254 Tel.: +801-585-9176     Fax: +801-581-5281 Email: kstevens@ece.utah.edu

Education

Professional Experience

Teaching Activities

University of Utah

Computer Design Lab: ECE/CS 3710

Computer Engineering Junior Seminar: CE 3991

Senior Pre-Thesis and Project: CE 3992

Computer Engineering Senior Project: CE 4710

Senior Project and Thesis I: ECE 4900

Senior Project and Thesis II: ECE 4910

Digital VLSI Design: ECE/CS 5710/6710

Relative Timed Asynchronous Design ECE/CS 5755/6755

Digital IC Project Testing: ECE/CS 6712

Advanced Digital VLSI: ECE/CS 6770

Designing Performance and Power Models for Communication Networks: ECE 5950/6950

Formal Verification and Model Checking of Hardware: ECE 6960

Air Force Institute of Technology

Asynchronous Systems and Circuits: EENG 899

Temporal Logic and Concurrent Processes: EENG 786/899

VLSI Design: EENG 695

Advanced Topics in VLSI: EENG 795

Research

VLSI, asynchronous circuit design and architecture, timing analysis, and formal verification.

• VLSI Circuit Design

  Digital CMOS VLSI provides a fantastic template for creating and engineering communication and control circuitry. Research focuses on architecture, circuit styles, and CAD. The Pentium front end is an example.

• Performance validation and CAD for multi-GHz circuits

  Many second order effects are becoming significant in multi-GHz circuits. A primary DSM effect studied is the variation created through multiple input switching (MIS), and how to generate and prune the worst case vectors. Research is also focused on evaluating and mitigating the effects of process variation.

• Relative Timing Verification

  Function and timing in circuits are highly interrelated. Verifying the timed behavior using timing variables has been relatively unsuccessful due to computational complexity. The novel Relative Timing research moves timing into the logic domain through relative logic relationships on the ordering of signal transitions. These techniques show order-of-magnitude improvement using SAT methods over the previous best approaches.

• Asynchronous Circuits and Systems

  Unclocked circuits have been designed to give significant improvement in performance, latency, and energy over designs with clocks, such as the Pentium front end and the post office chip. Research into correct application of this technology into system VLSI design and SOC integration shows further benefit.

• Communication Networks and Synchronization

  Current design technology favors design re-use. Integrating modules that run at various frequency and bandwidth requirements require flexible, high throughput, low latency communication networks that can synchronize different frequencies.

Links

• Class information, syllabus, handouts, etc.
• Publications that you can download
• Patent portfolio
• Public source for the International Spelling Checker for Emacsen]
• Public source for the MEAT Asynchronous Circuit Synthesis tool
• Public source for a relative timing verification engine]
• The post office communication chip developed at HP Labs]
• The RAPPID chip - an asynchronous Pentium front end

  
  

  ---

  Comments are welcome. Please send e-mail to kstevens@ece.utah.edu

  Copyright © 2005 - All rights reserved
  Last Modified:

  ---